The major and most common task in executing DSP algorithms is data processing in MAC (multiply-accumulate) loops. The majority of these MAC loops are within FIR (Finite Impulse Response) type algorithms. Many high-end DSP's are expected to use a dual-MAC structure to double their processing performance in the MAC loops. It is known that many applications require bit exactness. It also known that adding saturation logic for supporting bit exactness in dual-MAC is very expensive in area, timing critical path, and in power consumption.
Saturation arithmetic in a DSP is known, for example, from U.S. Pat. No. 3,812,470. This ubiquitous feature allows arithmetic combinations of values to saturate to a maximum value when signals become excessively strong (saturation in a DSP mimics the behavior of analog amplifiers, which are said to “rail out” at a maximum signal level; without saturation arithmetic in a DSP overflowing sums would ‘wrap around’—as only binary numbers—and produce unpredictable and undesirable outputs). In regular arithmetic, when an operation overflows or underflows (the result exceeds a maximum number of bits), the most significant bit is usually truncated (a process called ‘wrap-around’) and the remaining bits are used to produce the result, which may thus be significantly different from the value represented by the maximum number of bits (the ‘saturation’ value). Saturation arithmetic avoids this effect: instead of ‘wrapping around’ the result becomes the ‘saturation’ value. Saturation arithmetic is applicable in any area where a closest representable value in a result is preferable to a ‘wrap-around’ result.
However, although the additional hardware required for implementing a single-MAC with saturation capabilities may be considered acceptable, the additional hardware which is required for fully implementing a bit exact dual-MAC with saturation capabilities is significant and will impact timing critical path, chip area and power consumption. Although most new high-end DSP's have one or more dual-MAC units, it is expected that these will not support full dual-MAC bit exactness saturation capabilities. Avoidance of the high cost of support for full dual-MAC bit exactness saturation capabilities is a significant incentive to dropping this feature. The additional hardware requirements for implementing single-MAC and dual-MAC solutions with saturation capabilities are known, for example, from the paper by Yadav, Schulte and Glossner, titled “Parallel Saturating Fractional Arithmetic Units”, published in Proceedings of the 9th Great Lakes Symposium on VLSI, pp. 172–179, Ann Arbor, Mich., Mar. 4–6, 1999.
A need therefore exists for bit exactness support in dual-MAC architecture wherein the abovementioned disadvantage(s) may be alleviated.